Teaching GuideTerm Polytechnic University Collage |
Grao en Enxeñaría Electrónica Industrial e Automática |
Subjects |
Sistemas Dixitais I |
Assessment |
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Identifying Data | 2016/17 | |||||||||||||
Subject | Sistemas Dixitais I | Code | 770G01026 | |||||||||||
Study programme |
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Descriptors | Cycle | Period | Year | Type | Credits | |||||||||
Graduate | 2nd four-month period |
Third | Obligatoria | 6 | ||||||||||
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Methodologies | Competencies / Results | Description | Qualification |
Supervised projects | A3 A4 A5 A25 A30 A33 B1 B2 B3 B7 C2 C6 | Work designing a digital system of medium complexity. The correct application of theoretical concepts to the work performed will be evaluated. It is necessary to submit an explanatory report of it and make an oral presentation. | 50 |
Objective test | A26 A29 B1 | There will be 2 objective tests to be performed individually for each student. The first will take place once explained the first 5 issues. It will mean 25% of the final grade. The second test will be the final exam 1st opportunity and may have a weight of 25%, or 90%. |
50 |
Assessment comments | |||
The scores for the evaluable tasks are only valid for the academic year in which they are made. Objective tests may include short-answer questions and / or test, problem solving on paper or circuit design with the ISE software. To achieve maximum note at project designed circuits must work perfectly in all its aspects (functional and temporal simulation). Final grade The final grade is usually calculated as: Final grade = 0.25 x objective test 1 grade + 0.5 x project grade + 0,25 x objective test 2 grade Those students who do not have qualification in the 1st objective test, or, to resort very low scores can choose to make the 2nd objective test with a weight of 90% (the test will be different in this case). In this case the final grade will be: Final grade= 0.9 x objective test 2 grade Second opportunity The second time, an objective test that can consist of theoretical and practical questions, written exercises, issues and implementation of a circuit in one of the Laboratory boards will be performed. |
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