| Topic |
Sub-topic |
| Contidos da memoria de verificación relacionados cos temas da asignatura |
· Programación básica en VHDL: Temas 1 e 2.
· Deseño con dispositivos electrónicos configurables CPLD e FPGA: Temas 3, 4 e 6.
· Circuitos de memoria. Temas 5, 6 y 7.
· Conversión A/D y D/A. Tema 6 e 9.
· Ferramentas de deseño e desenvolvemento de sistemas lóxicos programables: Temas 4, 6, 8, 9 e 10.
· Transmisión de datos. Temas 8 y 10.
|
| Subject 1. Sequential syncronous systems design |
Finite state machines. Analysis and synthesis . VHDL description. |
| Subject 2. Introduction to Programmable Logic |
Programmable circuits features. Steps of design. Aplications. |
| Subject 3. PLD CoolRunner II architecture |
Function Blocks. Macrocells. I/O Blocks. Timming model. |
| Subject 4. Digital systems design with CPLDs. |
Synthesis: Examples of macros codes. Synthesis Report. Options. Translate. Fit:Options. Timming report
Secuencial systems design: Clock signals. Synchronous circuits design:counters, control circuits, asynchornous inputs, metaestability. Interface between synchronous systems and other circuits.
Design of complex systems: Method and practical application. |
| Subject 5. Architecture of the FPGAs of the family Spartan 3 E of Xilinx |
Logic resources.CLB. Internal memories. Clock Circuits. Multipliers. E/S technologies. |
| Subject 6. Synchronous design with FPGAs |
Synchronous design methodology. |
| Subject 7: Working with files |
File declaration. Reading and writing files. Open and close files. Package std_logic_textio. Examples. |
| Tema 8. Diseño de un controlador VGA |
DA converter for VGA into the Nexys 2. Standard VGA. Controller design. |
| Subject 8. Design of arithmetic systems with programmable logic |
Adders. Subtracters. Multipliers. Dividers
|
| Subject 9. Techniques for improving the performance of syncronous systems. |
Duplicating states. Pipelining. |
Subjects